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connection diagram 8-lead plastic mini-dip (n), cerdip (q) and soic (r) packages Cin r g Cv s +in r g +v s output ref 1 2 3 4 8 7 6 5 ad620 top view rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low cost, low power instrumentation amplifier ad620 features easy to use gain set with one external resistor (gain range 1 to 1000) wide power supply range ( 6 2.3 v to 6 18 v) higher performance than three op amp ia designs available in 8-lead dip and soic packaging low power, 1.3 ma max supply current excellent dc performance (b grade) 50 m v max, input offset voltage 0.6 m v/ 8 c max, input offset drift 1.0 na max, input bias current 100 db min common-mode rejection ratio (g = 10) low noise 9 nv/ ? hz , @ 1 khz, input voltage noise 0.28 m v p-p noise (0.1 hz to 10 hz) excellent ac specifications 120 khz bandwidth (g = 100) 15 m s settling time to 0.01% applications weigh scales ecg and medical instrumentation transducer interface data acquisition systems industrial process controls battery powered and portable equipment one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 product description the ad620 is a low cost, high accuracy instrumentation ampli- fier that requires only one external resistor to set gains of 1 to 0 5 10 15 20 30,000 5,000 10,000 15,000 20,000 25,000 0 total error, ppm of full scale supply current C ma ad620a r g 3 op-amp in-amp (3 op-07s) figure 1. three op amp ia designs vs. ad620 source resistance C v 100m 10k 1k 10m 1m 100k 10,000 0.1 100 1,000 10 1 rti voltage noise (0.1 C 10hz) C m v p-p typical standard bipolar input in-amp ad620 super b eta bipolar input in-amp g = 100 figure 2. total voltage noise vs. source resistance 1000. furthermore, the ad620 features 8-lead soic and dip packaging that is smaller than discrete designs, and offers lower power (only 1.3 ma max supply current), making it a good fit for battery powered, portable (or remote) applications. the ad620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 m v max and offset drift of 0.6 m v/ c max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. fur- thermore, the low noise, low input bias current, and low power of the ad620 make it well suited for medical applications such as ecg and noninvasive blood pressure monitors. the low input bias current of 1.0 na max is made possible with the use of super b eta processing in the input stage. the ad620 works well as a preamplifier due to its low input voltage noise of 9 nv/ ? hz at 1 khz, 0.28 m v p-p in the 0.1 hz to 10 hz band, 0.1 pa/ ? hz input current noise. also, the ad620 is well suited for multiplexed applications with its settling time of 15 m s to 0.01% and its cost is low enough to enable designs with one in- amp per channel.
ad620Cspecifications (typical @ +25 8 c, v s = 6 15 v, and r l = 2 k v , unless otherwise noted) ad620a ad620b ad620s 1 model conditions min typ max min typ max min typ max units gain g = 1 + (49.4 k/r g ) gain range 1 10,000 1 10,000 1 10,000 gain error 2 v out = 10 v g = 1 0.03 0.10 0.01 0.02 0.03 0.10 % g = 10 0.15 0.30 0.10 0.15 0.15 0.30 % g = 100 0.15 0.30 0.10 0.15 0.15 0.30 % g = 1000 0.40 0.70 0.35 0.50 0.40 0.70 % nonlinearity, v out = C10 v to +10 v, g = 1C1000 r l = 10 k w 10 40 10 40 10 40 ppm g = 1C100 r l = 2 k w 10 95 10 95 10 95 ppm gain vs. temperature g =1 10 10 10 ppm/ c gain >1 2 C50 C50 C50 ppm/ c voltage offset (total rti error = v osi + v oso /g) input offset, v osi v s = 5 v to 15 v 30 125 15 50 30 125 m v over temperature v s = 5 v to 15 v 185 85 225 m v average tc v s = 5 v to 15 v 0.3 1.0 0.1 0.6 0.3 1.0 m v/ c output offset, v oso v s = 15 v 400 1000 200 500 400 1000 m v v s = 5 v 1500 750 1500 m v over temperature v s = 5 v to 15 v 2000 1000 2000 m v average tc v s = 5 v to 15 v 5.0 15 2.5 7.0 5.0 15 m v/ c offset referred to the input vs. supply (psr) v s = 2.3 v to 18 v g = 1 80 100 80 100 80 100 db g = 10 95 120 100 120 95 120 db g = 100 110 140 120 140 110 140 db g = 1000 110 140 120 140 110 140 db input current input bias current 0.5 2.0 0.5 1.0 0.5 2 na over temperature 2.5 1.5 4 na average tc 3.0 3.0 8.0 pa/ c input offset current 0.3 1.0 0.3 0.5 0.3 1.0 na over temperature 1.5 0.75 2.0 na average tc 1.5 1.5 8.0 pa/ c input input impedance differential 10 i 210 i 210 i 2g w i pf common-mode 10 i 210 i 210 i 2g w i pf input voltage range 3 v s = 2.3 v to 5 v Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 Cv s + 1.9 +v s C 1.2 v over temperature Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 Cv s + 2.1 +v s C 1.3 v v s = 5 v to 18 v Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 Cv s + 1.9 +v s C 1.4 v over temperature Cv s + 2.1 +v s C 1.4 Cv s + 2.1 +v s C 1.4 Cv s + 2.3 +v s C 1.4 v common-mode rejection ratio dc to 60 hz with i k w source imbalance v cm = 0 v to 10 v g = 1 7390 8090 7390 db g = 10 93 110 100 110 93 110 db g = 100 110 130 120 130 110 130 db g = 1000 110 130 120 130 110 130 db output output swing r l = 10 k w , v s = 2.3 v to 5 v Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 Cv s + 1.1 +v s C 1.2 v over temperature Cv s + 1.4 +v s C 1.3 Cv s + 1.4 +v s C 1.3 Cv s + 1.6 +v s C 1.3 v v s = 5 v to 18 v Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 Cv s + 1.2 +v s C 1.4 v over temperature Cv s + 1.6 +v s C 1.5 Cv s + 1.6 +v s C 1.5 Cv s + 2.3 +v s C 1.5 v short current circuit 18 18 18 ma rev. e C2C
ad620 ad620a ad620b ad620s 1 model conditions min typ max min typ max min typ max units dynamic response small signal C3 db bandwidth g = 1 1000 1000 1000 khz g = 10 800 800 800 khz g = 100 120 120 120 khz g = 1000 12 12 12 khz slew rate 0.75 1.2 0.75 1.2 0.75 1.2 v/ m s settling time to 0.01% 10 v step g = 1C100 15 15 15 m s g = 1000 150 150 150 m s noise voltage noise, 1 khz total rti noise = ( e 2 ni ) + ( e no / g ) 2 input, voltage noise, e ni 913 913 913 nv/ ? hz output, voltage noise, e no 72 100 72 100 72 100 nv/ ? hz rti, 0.1 hz to 10 hz g = 1 3.0 3.0 6.0 3.0 6.0 m v p-p g = 10 0.55 0.55 0.8 0.55 0.8 m v p-p g = 100C1000 0.28 0.28 0.4 0.28 0.4 m v p-p current noise f = 1 khz 100 100 100 fa/ ? hz 0.1 hz to 10 hz 10 10 10 pa p-p reference input r in 20 20 20 k w i in v in+ , v ref = 0 +50 +60 +50 +60 +50 +60 m a voltage range Cv s + 1.6 +v s C 1.6 Cv s + 1.6 +v s C 1.6 Cv s + 1.6 +v s C 1.6 v gain to output 1 0.0001 1 0.0001 1 0.0001 power supply operating range 4 2.3 18 2.3 18 2.3 18 v quiescent current v s = 2.3 v to 18 v 0.9 1.3 0.9 1.3 0.9 1.3 ma over temperature 1.1 1.6 1.1 1.6 1.1 1.6 ma temperature range for specified performance C40 to +85 C40 to +85 C55 to +125 c notes 1 see analog devices military data sheet for 883b tested specifications. 2 does not include effects of external resistor r g . 3 one input grounded. g = 1. 4 this is defined as the same supply range which is used to specify psr. specifications subject to change without notice. rev. e C3C
ad620 rev. e C4C notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic package: q ja = 95 c/w 8-lead cerdip package: q ja = 110 c/w 8-lead soic package: q ja = 155 c/w absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . . 650 mw input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 25 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite storage temperature range (q) . . . . . . . . . . C65 c to +150 c storage temperature range (n, r) . . . . . . . . C65 c to +125 c operating temperature range ad620 (a, b) . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c ad620 (s) . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300 c ordering guide model temperature ranges package options* ad620an C40 c to +85 c n-8 ad620bn C40 c to +85 c n-8 ad620ar C40 c to +85 c so-8 ad620ar-reel C40 c to +85 c 13" reel ad620ar-reel7 C40 c to +85 c 7" reel ad620br C40 c to +85 c so-8 AD620BR-REEL C40 c to +85 c 13" reel AD620BR-REEL7 C40 c to +85 c 7" reel ad620achips C40 c to +85 c die form ad620sq/883b C55 c to +125 c q-8 *n = plastic dip; q = cerdip; so = small outline. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions. +v s output reference +in Cv s Cin *for chip applications: the pads 1r g and 8r g must be connected in parallel to the external gain register r g . do not connect them in series to r g . for unity gain applications where r g is not required, the pads 1r g may simply be bonded together, as well as the pads 8r g . 4 5 6 7 8 8 r g * 1 1 2 3 r g * 0.125 (3.180) 0.0708 (1.799) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad620 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad620 rev. e C5C typical characteristics (@ +25 8 c, v s = 6 15 v, r l = 2 k v , unless otherwise noted) input offset voltage C m v 20 30 40 50 C40 0 +40 +80 percentage of units C80 sample size = 360 10 0 figure 3. typical distribution of input offset voltage input bias current C pa 0 10 20 30 40 50 C600 0 +600 percentage of units C1200 +1200 sample size = 850 figure 4. typical distribution of input bias current 10 20 30 40 50 C200 0 +200 +400 input offset current C pa percentage of units C400 0 sample size = 850 figure 5. typical distribution of input offset current temperature C 8 c input bias current C na +i b Ci b 2.0 C2.0 175 C1.0 C1.5 C75 C0.5 0 0.5 1.0 1.5 125 75 25 C25 figure 6. input bias current vs. temperature change in offset voltage C m v 1.5 0.5 warm-up time C minutes 2 0 05 1 1 4 3 2 figure 7. change in input offset voltage vs. warm-up time frequency C hz 1000 1 1 100k 100 10 10k 1k 100 voltage noise C nv/ ! hz gain = 1 gain = 10 10 gain = 100, 1,000 gain = 1000 bw limit figure 8. voltage noise spectral density vs. frequency, (g = 1C1000)
ad620Ctypical characteristics frequency C hz 1000 100 10 1 10 1000 100 current noise C fa/ ! hz figure 9. current noise spectral density vs. frequency rti noise C 2.0 m v/div time C 1 sec/div figure 10a. 0.1 hz to 10 hz rti voltage noise (g = 1) rti noise C 0.1 m v/div time C 1 sec/div figure 10b. 0.1 hz to 10 hz rti voltage noise (g = 1000) figure 11. 0.1 hz to 10 hz current noise, 5 pa/div 100 1000 ad620a fet input in-amp source resistance C v total drift from 25 8 c to 85 8 c, rti C m v 100,000 10 1k 10m 10,000 10k 1m 100k figure 12. total drift vs. source resistance frequency C hz cmr C db +160 0 1m +80 +40 1 +60 0.1 +140 +100 +120 100k 10k 1k 100 10 g = 1000 g = 100 g = 10 g = 1 +20 figure 13. cmr vs. frequency, rti, zero to 1 k w source imbalance rev. e C6C
ad620 rev. e C7C frequency C hz psr C db 160 1m 80 40 1 60 0.1 140 100 120 100k 10k 1k 100 10 20 g = 1000 g = 100 g = 10 g = 1 180 figure 14. positive psr vs. frequency, rti (g = 1C1000) frequency C hz psr C db 160 1m 80 40 1 60 0.1 140 100 120 100k 10k 1k 100 10 20 180 g = 10 g = 100 g = 1 g = 1000 figure 15. negative psr vs. frequency, rti (g = 1C1000) 1000 100 10m 100 1 1k 10 100k 1m 10k frequency C hz gain C v/v 0.1 figure 16. gain vs. frequency output voltage C volts p-p frequency C hz 35 0 1m 15 5 10k 10 1k 30 20 25 100k g = 10, 100, 1000 g = 1 g = 1000 g = 100 bw limit figure 17. large signal frequency response input voltage limit C volts (referred to supply voltages) 20 +1.0 +0.5 5 0 +1.5 C1.5 C1.0 C0.5 15 10 supply voltage 6 volts +v s C0.0 Cv s +0.0 figure 18. input voltage range vs. supply voltage, g = 1 20 +1.0 +0.5 5 0 +1.5 C1.5 C1.0 C0.5 15 10 supply voltage 6 volts r l = 10k v r l = 2k v r l = 10k v output voltage swing C volts (referred to supply voltages) r l = 2k v +v s C0.0 Cv s +0.0 figure 19. output voltage swing vs. supply voltage, g = 10
ad620 rev. e C8C output voltage swing C volts p-p load resistance C v 30 0 0 10k 20 10 100 1k v s = 6 15v g = 10 figure 20. output voltage swing vs. load resistance ........ .................... ............ ........ .................... ............ figure 21. large signal pulse response and settling time g = 1 (0.5 mv = 0.01%) .... ........................ ............ .... ........................ ............ figure 22. small signal response, g = 1, r l = 2 k w , c l = 100 pf .... ........................ ............ .... ........................ ............ figure 23. large signal response and settling time, g = 10 (0.5 mv = 001%) ........ .................... ............ ........ .................... ............ figure 24. small signal response, g = 10, r l = 2 k w , c l = 100 pf .... ........................ .... ........ .... ........................ .... ........ figure 25. large signal response and settling time, g = 100 (0.5 mv = 0.01%)
ad620 rev. e C9C .... ........................ .... ........ .... ........................ .... ........ figure 26. small signal pulse response, g = 100, r l = 2 k w , c l = 100 pf ........ .................... ............ ........ .................... ............ figure 27. large signal response and settling time, g = 1000 (0.5 mv = 0.01%) .... ........................ .... ........ .... ........................ .... ........ figure 28. small signal pulse response, g = 1000, r l = 2 k w , c l = 100 pf output step size C volts settling time C m s to 0.01% to 0.1% 20 0 020 15 5 5 10 10 15 figure 29. settling time vs. step size (g = 1) gain settling time C m s 1000 1 1 1000 100 10 10 100 figure 30. settling time to 0.01% vs. gain, for a 10 v step ........ .................... ............ ........ .................... ............ figure 31a. gain nonlinearity, g = 1, r l = 10 k w (10 m v = 1 ppm)
ad620 rev. e C10C v b Cv s a1 a2 a3 c2 r g r1 r2 gain sense gain sense r3 400 v 10k v 10k v i2 i1 10k v ref 10k v +in C in 20 m a 20 m a r4 400 v output c1 q2 q1 figure 33. simplified schematic of ad620 theory of operation the ad620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. absolute value trimming allows the user to program gain accurately (to 0.15% at g = 100) with only one resistor. monolithic construc- tion and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. the input transistors q1 and q2 provide a single differential- pair bipolar input for high precision (figure 33), yet offer 10 lower input bias current thanks to super b eta processing. feed- back through the q1-a1-r1 loop and the q2-a2-r2 loop main- tains constant collector current of the input devices q1, q2 thereby impressing the input voltage across the external gain setting resistor r g . this creates a differential gain from the inputs to the a1/a2 outputs given by g = (r1 + r2)/r g + 1. the unity-gain subtracter a3 removes any common-mode sig- nal, yielding a single-ended output referred to the ref pin potential. the value of r g also determines the transconductance of the preamp stage. as r g is reduced for larger gains, the transcon- ductance increases asymptotically to that of the input transist ors. this has three important advantages: (a) open-loop gain is boosted for increasing programmed gain, thus reducing gain- related errors. (b) the gain-bandwidth product (determined by c1, c2 and the preamp transconductance) increases with pro- grammed gain, thus optimizing frequency response. (c) the input voltage noise is reduced to a value of 9 nv/ ? hz , deter- mined mainly by the collector current and base resistance of the input devices. the internal gain resistors, r1 and r2, are trimmed to an abso- lute value of 24.7 k w , allowing the gain to be programmed accurately with a single external resistor. the gain equation is then g = 49.4 k w r g + 1 so that r g = 49.4 k w g - 1 .... ............................ ........ .... ............................ ........ figure 31b. gain nonlinearity, g = 100, r l = 10 k w (100 m v = 10 ppm) .... .... ........................ ........ .... .... ........................ ........ figure 31c. gain nonlinearity, g = 1000, r l = 10 k w (1 mv = 100 ppm) ad620 v out g=1 g=1000 49.9 v 10k v * 1k v 10t 10k v 499 v g=10 g=100 5.49k v +v s 11k v 1k v 100 v 100k v input 10v p-p Cv s *all resistors 1% tolerance 7 1 2 3 8 6 4 5 figure 32. settling time test circuit
ad620 rev. e C11C make vs. buy: a typical bridge application error budget the ad620 offers improved performance over homebrew three op amp ia designs, along with smaller size, fewer compo- nents and 10 lower supply current. in the typical application, shown in figure 34, a gain of 100 is required to amplify a bridge output of 20 mv full scale over the industrial temperature range of C40 c to +85 c. the error budget table below shows how to calculate the effect various error sources have on circuit accuracy. regardless of the system in which it is being used, the ad620 provides greater accuracy, and at low power and price. in simple r = 350 v +10v precision bridge transducer ad620a monolithic instrumentation amplifier, g = 100 homebrew in-amp, g = 100 *0.02% resistor match, 3ppm/ 8 c tracking **discrete 1% resistor, 100ppm/ 8 c tracking supply current = 15ma max 100 v ** 10k v * 10k v ** 10k v * 10k v * 10k v ** 10k v * supply current = 1.3ma max op07d op07d op07d ad620a r g 499 v reference r = 350 v r = 350 v r = 350 v figure 34. make vs. buy table i. make vs. buy error budget ad620 circuit homebrew circuit error, ppm of full scale error source calculation calculation ad620 homebrew absolute accuracy at t a = +25 c input offset voltage, m v 125 m v/20 mv (150 m v ? 2 )/20 mv 1 6,250 10,607 output offset voltage, m v 1000 m v/100/20 mv ((150 m v 2)/100)/20 mv 14, 500 10, 150 input offset current, na 2 na 350 w /20 mv (6 na 350 w )/20 mv 14,1 18 14,1 53 cmr, db 110 db ? 3.16 ppm, 5 v/20 mv (0.02% match 5 v)/20 mv/100 14, 791 10, 500 total absolute error 1 7,558 11,310 drift to +85 c gain drift, ppm/ c (50 ppm + 10 ppm) 60 c 100 ppm/ c track 60 c 1 3,600 1 6,000 input offset voltage drift, m v/ c1 m v/ c 60 c/20 mv (2.5 m v/ c ? 2 60 c)/20 mv 1 3,000 10,607 output offset voltage drift, m v/ c 15 m v/ c 60 c/100/20 mv (2.5 m v/ c 2 60 c)/100/20 mv 14, 450 10, 150 total drift error 1 7,050 16,757 resolution gain nonlinearity, ppm of full scale 40 ppm 40 ppm 14,1 40 10,1 40 typ 0.1 hzC10 hz voltage noise, m v p-p 0.28 m v p-p/20 mv (0.38 m v p-p ? 2 )/20 mv 141, 14 13,1 27 total resolution error 14,1 54 101, 67 grand total error 14,662 28,134 g = 100, v s = 15 v. (all errors are min/max and referred to input.) systems, absolute accuracy and drift errors are by far the most significant contributors to error. in more complex systems with an intelligent processor, an autogain/autozero cycle will remove all absolute accuracy and drift errors leaving only the resolution errors of gain nonlinearity and noise, thus allowing full 14-bit accuracy. note that for the homebrew circuit, the op07 specifications for input voltage offset and noise have been multiplied by ? 2 . this is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error.
ad620 rev. e C12C 3k v +5v digital data output adc ref in agnd 20k v 10k v 20k v ad620b g=100 1.7ma 0.10ma 0.6ma max 499 v 3k v 3k v 3k v 2 1 8 3 7 6 5 4 1.3ma max ad705 figure 35. a pressure monitor circuit which operates on a +5 v single supply pressure measurement although useful in many bridge applications such as weigh scales, the ad620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. figure 35 shows a 3 k w pressure transducer bridge powered from +5 v. in such a circuit, the bridge consumes only 1.7 ma. adding the ad620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 ma of total supply current. small size and low cost make the ad620 especially attractive for voltage output pressure transducers. since it delivers low noise and drift, it will also serve applications such as diagnostic non- invasive blood pressure measurement. medical ecg the low current noise of the ad620 allows its use in ecg monitors (figure 36) where high source resistances of 1 m w or higher are not uncommon. the ad620s low power, low supply voltage requirements, and space-saving 8-lead mini-dip and soic package offerings make it an excellent choice for battery powered data recorders. furthermore, the low bias currents and low current noise coupled with the low voltage noise of the ad620 improve the dynamic range for better performance. the value of capacitor c1 is chosen to maintain stability of the right leg drive loop. proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. g = 7 ad620a 0.03hz high pass filter output 1v/mv +3v C3v r g 8.25k v 24.9k v 24.9k v ad705j g = 143 c1 1m v r4 10k v r1 r3 r2 output amplifier patient/circuit protection/isolation figure 36. a medical ecg monitor circuit
ad620 rev. e C13C precision v-i converter the ad620, along with an other op amp and two resistors, makes a precision current source (figure 37). the op amp buffers the reference terminal to maintain good cmr. the output voltage v x of the ad620 appears across r1, which converts it to a curre nt. this current less only, the input bias current of the op amp, then flows out to the load. ad620 r g Cv s v in+ v inC load r1 i l v x i = l r1 = in+ [(v ) C (v )] g inC r1 6 5 + v C x 4 2 1 8 3 7 +v s ad705 figure 37. precision voltage-to-current converter (operates on 1.8 ma, 3 v) gain selection the ad620s gain is resistor programmed by r g , or more pre- cisely, by whatever impedance appears between pins 1 and 8. the ad620 is designed to offer accurate gains using 0.1%C1% resistors. table ii shows required values of r g for various gains. note that for g = 1, the r g pins are unconnected (r g = ). for any arbitrary gain r g can be calculated by using the formula: r g = 49.4 k w g - 1 to minimize gain error, avoid high parasitic resistance in series with r g ; to minimize gain drift, r g should have a low tcless than 10 ppm/ cfor the best performance. table ii. required values of gain resistors 1% std table calculated 0.1% std table calculated value of r g , v gain value of r g , v gain 49.9 k 1.990 49.3 k 2.002 12.4 k 4.984 12.4 k 4.984 5.49 k 9.998 5.49 k 9.998 2.61 k 19.93 2.61 k 19.93 1.00 k 50.40 1.01 k 49.91 499 100.0 499 100.0 249 199.4 249 199.4 100 495.0 98.8 501.0 49.9 991.0 49.3 1,003 input and output offset voltage the low errors of the ad620 are attributed to two sources, input and output errors. the output error is divided by g when referred to the input. in practice, the input errors dominate at high gains and the output errors dominate at low gains. the total v os for a given gain is calculated as: total error rti = input error + (output error/g) total error rto = (input error g) + output error reference terminal the reference terminal potential defines the zero output voltage, and is especially useful when the load does not share a precise ground with the rest of the system. it provides a direct means of injecting a precise offset to the output, with an allowable range of 2 v within the supply voltages. parasitic resistance should be kept to a minimum for optimum cmr. input protection the ad620 features 400 w of series thin film resistance at its inputs, and will safely withstand input overloads of up to 15 v or 60 ma for several hours. this is true for all gains, and power on and off, which is particularly important since the signal source and amplifier may be powered separately. for longer time periods, the current should not exceed 6 ma (i in v in /400 w ). for input overloads beyond the supplies, clamping the inputs to the supplies (using a low leakage diode such as an fd333) will reduce the required resistance, yielding lower noise. rf interference all instrumentation amplifiers can rectify out of band signals, and when amplifying small signals, these rectified voltages act as small dc offset errors. the ad620 allows direct access to the input transistor bases and emitters enabling the user to apply some first order filtering to unwanted rf signals (figure 38), where rc < 1/(2 p f) and where f 3 the bandwidth of the ad620; c 150 pf. matching the extraneous capacitance at pins 1 and 8 and pins 2 and 3 helps to maintain high cmr. Cin 1 2 3 4 5 6 7 8 r r +in c c r g figure 38. circuit to attenuate rf interference
ad620 rev. e C14C common-mode rejection instrumentation amplifiers like the ad620 offer high cmr, which is a measure of the change in output voltage when both inputs are changed by equal amounts. these specifications are usually given for a full-range input voltage change and a speci- fied source imbalance. for optimal cmr the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. in many applications shielded cables are used to minimize noise, and for best cmr over frequency the shield should be properly driven. figures 39 and 40 show active data guards that are configured to improve ac common-mode rejections by bootstrapping the capacitances of input cable shields, thus minimizing the capaci- tance mismatch between the inputs. reference v out ad620 100 v 100 v C input + input ad648 r g Cv s +v s Cv s figure 39. differential shield driver 100 v C input + input reference v out ad620 Cv s +v s 2 r g 2 r g ad548 figure 40. common-mode shield driver grounding since the ad620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the ref pin to the appropriate local ground. in order to isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (figure 41). it would be conve- nient to use a single ground line; however, current through ground wires and pc runs of the circuit card can cause hun- dreds of millivolts of error. therefore, separate ground returns should be provided to minimize the current flow from the sensi- tive points to the system ground. these ground returns must be tied together at some point, usually best at the adc package as shown. digital p.s. +5v c analog p.s. +15v c C15v ad574a digital data output + 1 m f ad620 0.1 m f ad585 s/h adc 0.1 m f 1 m f 1 m f figure 41. basic grounding practice
ad620 rev. e C15C ground returns for input bias currents input bias currents are those currents necessary to bias the input transistors of an amplifier. there must be a direct return path for these currents; therefore, when amplifying floating input v out ad620 C input r g to power supply ground reference + input +v s Cv s load figure 42a. ground returns for bias currents with transformer coupled inputs sources such as transformers, or ac-coupled sources, there must be a dc path from each input to ground as shown in figure 42. refer to the instrumentation amplifier application guide (free from analog devices) for more information regarding in amp applications. v out C input + input r g load to power supply ground reference +v s Cv s ad620 figure 42b. ground returns for bias currents with thermocouple inputs 100k v v out ad620 C input + input r g load to power supply ground reference 100k v Cv s +v s figure 42c. ground returns for bias currents with ac coupled inputs
ad620 rev. e C16C outline dimensions dimensions shown in inches and (mm). plastic dip (n-8) package 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) cerdip (q-8) package 8 1 4 5 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.4) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 0.405 (10.29) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) soic (so-8) package 0.1968 (5.00) 0.1890 (4.80) 85 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 c1599cC0C7/99 printed in u.s.a.

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